This invention generally relates to chemical mechanical polishing (CMP) and more particularly to a method for preventing copper (Cu) corrosion due to localized chemical potentials during a chemical mechanical polishing (CMP) process.
In semiconductor fabrication integrated circuits and semiconducting devices are formed by sequentially forming features in sequential layers of material in a bottom-up manufacturing method. The manufacturing process utilizes a wide variety of deposition techniques to form the various layered features including various etching techniques such as anisotropic plasma etching to form device feature openings followed by deposition techniques to fill the device features. In order to form reliable devices, close tolerances are required in forming features including photolithographic patterning methods which rely heavily on layer planarization techniques to maintain a proper depth of focus.
Planarization is increasingly important in semiconductor manufacturing techniques. As device sizes decrease, the importance of achieving high resolution features through photolithographic processes correspondingly increases thereby placing more severe constraints on the degree of planarity required of a semiconductor wafer processing surface. Excessive degrees of surface nonplanarity will undesirably affect the quality of several semiconductor manufacturing process including, for example, photolithographic patterning processes, where the positioning the image plane of the process surface within an increasingly limited depth of focus window is required to achieve high resolution semiconductor feature patterns.
In the formation of conductive interconnections, copper is increasingly used for forming metal interconnects such as vias and trench lines since copper has low resistivity and good electromigration resistance compared to other traditional interconnect metals such as aluminum. The undesirable contribution to electrical parasitic effects by metal interconnect residual resistivity has become increasingly important as device sizes have decreased.
Chemical mechanical polishing (CMP) is increasingly being used as a planarizing process for semiconductor device layers, especially for devices having multi-level design and smaller semiconductor fabrication processes, for example, having line widths below about 0.25 micron. CMP planarization is typically used several different times in the manufacture of a multi-level semiconductor device, including planarizing levels of a device containing both dielectric and metal portions to achieve global planarization for subsequent processing of overlying levels. For example, CMP is used to remove excess metal after filling conductive metal interconnect openings formed in dielectric insulating layers with metal to form features such as vias and trench lines. The vias and trench lines electrically interconnect the several levels and areas within a level that make up a multi-level semiconductor device.
In a typical process for forming conductive interconnections in a multi-level semiconductor device, a damascene process is used to form vias and trench lines for interconnecting different levels and areas within levels of the multi-level device. Vias (e.g., V1, V2 etc. lines) are generally used for vertically electrically interconnecting semiconductor device levels and trench lines (e.g., M1, M2, etc. lines) are used for electrically interconnecting semiconductor device areas within a level. Vias and trench lines are typically formed as part of a damascene process. Although there are several different methods for forming damascene structures, one typical method generally involves patterning and anisotropically etching a semiconductor feature, for example a via opening within an dielectric insulating layer to form closed communication with a conductive area included in an underlying level of the multi-level device. A similar process is then used to pattern and anisotropically etch a trench line opening overlying and encompassing the via opening to form a dual damascene opening structure. The dual damascene structure is then filled with a metal, for example copper, followed by a CMP step to remove excess copper overlying the dielectric insulating layer, also referred to as an inter-metal dielectric (IMD) layer surface, and to planarize the IMD layer surface for subsequent formation of an overlying device level. The process is then repeated in an overlying IMD layer to form a series of stacked conductive lines which electrically communicate between and within the various layers to form a multi-level semiconductor device. Typically, vias and dual damascene structures are stacked above one another to reduce an overall space requirement for patterning a semiconductor device.
CMP generally includes mechanical polishing assisted by chemical action to achieve selective material removal. CMP generally includes mounting wafer on a carrier with the wafer process surface face-down to contact a flat polishing surface, typically a polishing pad mounted on a rotating platen, imparting a downforce to the wafer backside and moving the wafer and the polishing surface relative to one another. The polishing action is typically aided by a slurry which includes for example, small abrasive particles such as silica (SiO2), alumina (Al2O3), and ceria (CeO2) that abrasively act to remove a portion of the process surface. Additionally, the slurry may include chemicals such as complexing agents and film forming agents that react with the process surface to assist in removing a portion of the surface material, the slurry typically being introduced to contact the polishing pad and thereby the wafer process surface.
Several semiconductor feature defects can be associated with CMP polishing. For example, in CMP polishing metals, for example copper features included in an array of metal interconnects, the copper is removed or eroded at a faster rate than the surrounding field of insulating dielectric. This causes a topography difference between insulating dielectric and the dense copper array. Such erosion can lead to excess removal of copper such that overlying formation of electrical interconnecting features, for example, stacked vias, leads to electrical failure by causing discontinuous electrical communication pathways.
Another CMP induce defect is related to the formation of copper interconnect features such as copper filled vias and trenches and the practice of forming a conformal barrier/adhesion layer within the anisotropically etched features prior to filling with copper. The barrier/adhesion layer is formed to prevent diffusion of copper into the dielectric insulating layer (IMD) within which the vias and trench openings are formed. The barrier/adhesion layer typically includes a refractory metal such as Tantalum (Ta) or refractory metal nitride such as tantalum nitride (TaN). After filling of the anisotropically etched features with copper, for example by electroplating, a CMP process is carried out to first remove the excess copper overlying the barrier/adhesion layer and another CMP process performed to remove the barrier/adhesion layer overlying the IMD layer. During a portion of the CMP process, for example where both copper and barrier/adhesion material are exposed on the polishing surface, it is believed that a corrosive electrochemical reaction due to charge accumulation on the wafer surface and the presence of two dissimilar metals, for example tantalum and copper, results in corrosion of copper containing features. It is believed that the corrosive electrochemical reaction is due at least in part to locally induced Galvanic chemical potentials at the wafer surface, for example, at the copper/barrier layer interface where both the barrier layer and copper features are exposed to the polishing slurry.
For example, referring to FIG. 1 is shown a portion of a multi-level semiconductor device including dual damascene structures e.g., 10, 12 and 13, 15 forming stacked dual damascene structures. The stacked dual damascene structures include a via portion e.g., 10A,12A and a trench line portion e.g., 10B, 12B, formed in a first IMD layer 14A and a second IMD layer 14B. After patterning and anisotropically etching the via and trench openings in IMD 14A, a barrier/adhesion layer of for example, tantalum nitride, 16A, is conformally deposited to line the dual damascene structure prior to filling with copper, e.g., 18A, for example by an electrodeposition process. Following the copper filling process, a CMP process is carried out to polish back excess copper and the underlying barrier/adhesion layer formed over the IMD layer 14A surface (not shown) to planarize the IMD layer 14A prior to forming the overlying IMD layer 14B to form another overlying dual damascene structure, e.g., 12. During the CMP process, copper corrosion of the upper portion of, for example, trench line e.g., 10BA, 12B, may take place by electrochemical corrosion forming recessed areas in the upper portion of the trench lines e.g., 10B, 12B, devoid of copper filling e.g., as shown at e.g., 10C, 12C thereby inducing an open circuit in the electrical interconnect.
According To the prior art, several approaches have been proposed to reduce the copper corrosion action that takes place during CMP. One approach has been to add film forming agents or corrosion inhibitors to the slurry solution to inhibit the polishing of the copper surfaces. A problem with this approach is that the polishing rate of copper is frequently slowed to an excessive extent causing an undesirable increase in throughput times and slurry usage. In addition, the problem of localized electrochemical potentials on the wafer surface remains causing electrochemical corrosion of copper containing semiconductor features. Other approaches have included performing the CMP polishing process in a black box as it has been believed that localized electrochemical potentials were related to the production of electron-hole pairs from incident light. None of these approaches had been fully effective in eliminating copper corrosion of copper containing semiconductor features during CMP.
Therefore, there is a need in the semiconductor art to develop a CMP method for planarizing dielectric layers including copper semiconductor features such that CMP induced defects such as copper corrosion are reduced or prevented without undesirably slowing material removal rates.
It is therefore an object of the invention to provide a CMP method for planarizing dielectric layers including copper semiconductor features such that CMP induced defects such as copper corrosion are reduced or prevented without undesirably slowing material removal rates while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for preventing or reducing corrosion of copper containing semiconductor features during chemical mechanical polishing (CMP).
In a first embodiment, the method includes providing a semiconductor wafer polishing surface including a copper layer overlying a copper filled anisotropically etched feature; polishing the semiconductor wafer polishing surface according to a first CMP process including applying at least one polishing slurry to contact the semiconductor wafer polishing surface to remove at least a portion the copper layer to reveal a portion of an underlying barrier/adhesion layer; polishing the semiconductor wafer polishing surface according to a second CMP process including applying a neutralizing solution to contact the semiconductor wafer polishing surface to neutralize a semiconductor wafer polishing surface including chemical potentials; polishing the semiconductor wafer polishing surface according to a third CMP process including applying a copper corrosion inhibitor solution to contact the semiconductor wafer polishing surface to inhibit copper corrosion; and, polishing the semiconductor wafer polishing surface according to at least a to fourth CMP process to remove a remaining portion of the underlying barrier/adhesion layer.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.